Subject matter disclosed herein relates to memory devices and, more particularly, to apparatuses, devices, and methods for sensing a snapback event of a circuit.
A memory device may comprise a plurality of memory cells. For example, a plurality of memory cells may be arranged in an array configuration and/or a stacked configuration. A memory device may also comprise an interface that may be used, for example, in accessing a memory cell. For example, an interface may access a memory cell to determine a programmed state of the memory cell, e.g., as part of a READ operation. For example, an interface may access a memory cell to establish a programmed state in the memory cell, e.g., as part of a WRITE operation. An interface may, for example, be coupled to one or more other circuit devices (e.g., a processor, a transceiver, etc.), which may use a memory device.
In certain example instances, a memory device may be provided as a separate component (e.g., chip, semiconductor die, etc.) which may be coupled to other circuit devices. In certain other instances, a memory device may be provided along with one or more other circuit devices, for example, as part of multiple chip package, one or more semiconductor dies, a system on a chip, just to name a few.
In certain instances, a memory device may comprise a phase change memory (PCM). In certain instances, a memory cell may comprise PCM component (e.g., a chalcogenic component such as an ovonic memory switch (OMS), etc.) and a selection component (e.g., a thresholding component such as an ovonic threshold switch (OTS)). Such a memory cell may, for example, be referred to as a PCM and Switch (PCMS) memory cell.